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SH7265 датащи(PDF) 73 Page - Renesas Technology Corp

номер детали SH7265
подробное описание детали  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  2024 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7265 датащи(HTML) 73 Page - Renesas Technology Corp

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Section 1
Overview
Rev. 1.00 Mar. 14, 2008 Page 37 of 1984
REJ09B0351-0100
Classification
Symbol
I/O
Name
Function
Operating mode
control
ASEMD
I
ASE mode
During
RES pin assertion period,
input a low level to operate this LSI
in ASE mode. To operate it in
product chip mode, apply a high
level to this pin.
Enables the E10A-USB emulator
functions in ASE mode.
Fix a high level mode when not using
emulator functions.
RES
I
Power-on reset
This LSI enters the power-on reset
state when this signal goes low.
MRES
I
Manual reset
This LSI enters the manual reset
state when this signal goes low.
System control
WDTOVF
O
Watchdog timer
overflow
Outputs an overflow signal from the
WDT.
NMI
I
Non-maskable
interrupt
Non-maskable interrupt request pin.
Fix it high when not in use.
IRQ7 to IRQ0
I
Interrupt requests
7 to 0
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Interrupts
PINT7 to PINT0 I
Interrupt requests
7 to 0
Maskable interrupt request pins.
Only level-input detection can be
selected.
User break
controller (UBC)
UBCTRG
O
User break
trigger output
Trigger output pin for UBC condition
match.
Address bus
A25 to A0
O
Address bus
Outputs addresses.
Data bus
D31 to D0
I/O
Data bus
Bidirectional data bus.



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