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SH7265 датащи(PDF) 86 Page - Renesas Technology Corp

номер детали SH7265
подробное описание детали  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
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производитель  RENESAS [Renesas Technology Corp]
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SH7265 датащи(HTML) 86 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 1.00 Mar. 14, 2008 Page 50 of 1984
REJ09B0351-0100
2.1.3
System Registers
The system registers consist of four 32-bit registers: the high and low multiply and accumulate
registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH
and MACL store the results of multiply or multiply and accumulate operations. PR stores the
return address from a subroutine procedure. PC indicates the four bytes ahead of the current
instruction being executed.
31
0
31
0
31
PC
PR
MACL
MACH
Multiply and accumulate register high (MACH) and multiply
and accumulate register low (MACL):
Store the results of multiply or multiply and accumulate operations.
Procedure register (PR):
Stores the return address from a subroutine procedure.
Program counter (PC):
Indicates the four bytes ahead of the current instruction.
0
Figure 2.3 System Registers
(1)
Multiply and Accumulate Register High (MACH) and Multiply and Accumulate
Register Low (MACL)
MACH and MACL are used as the addition value in a MAC instruction, and store the result of a
MAC or MUL instruction.
(2)
Procedure Register (PR)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is
referenced by a subroutine return instruction (RTS).
(3)
Program Counter (PC)
PC indicates the four bytes ahead of the current instruction being executed.



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