SH7265 datasheet(39/2024 Pages) RENESAS

39 / 2024 page

Section 1

Overview

Rev. 1.00 Mar. 14, 2008 Page 3 of 1984

REJ09B0351-0100

Items

Specification

Floating-point unit

(FPU)

• Floating-point co-processor included

• Supports single-precision (32-bit) and double-precision (64-bit)

• Supports data types and exceptions that conform to IEEE754 standard

• Two rounding modes: Round to the nearest and round to zero

• Handling of denormalized numbers: Flush to zero

• Floating-point registers

 Sixteen 32-bit floating-point registers (single-precision × 16 words

or double-precision

× 8 words)

 Two 32-bit floating-point system registers

• Supports FMAC (multiplication and accumulation) instruction

• Supports FDIV (division) and FSQRT (square root) instructions

• Supports FLDI0/FLDI1 (load constant 0/1) instructions

• Instruction execution time

 Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-

precision), eight cycles (double-precision)

 Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six

cycles (double-precision)

Note: FMAC only supports single-precision

• Five-stage pipeline

Exclusive control and

memory sharing

• Supports exclusive control between two CPUs

Semaphore control through registers provided between two CPUs

Exclusive control by TAS.B instruction

Clock pulse generator

(CPG)

• Clock mode: Input clock source can be selected from external input

(EXTAL, CKIO, or USB_X1) or crystal resonator

• Input clock can be multiplied by 16 (max.) by the internal PLL circuit

• Four types of clocks generated:

 CPU0 clock: Maximum 200 MHz

 CPU1 clock: Maximum 200 MHz

 Bus clock: Maximum 66 MHz (CPU0 bus, CPU1 bus and peripheral

buses 1, 2, 3)

 Peripheral clock: Maximum 33 MHz (peripheral bus 0)

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