SH-2 datasheet(15/919 Pages) RENESAS

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9.4.3

Example of DMA Transfer between External Memory and SCI1 Transmitting Side

(Indirect Address On) ........................................................................................... 170

9.5

Usage Notes ....................................................................................................................... 172

Section 10 Advanced Timer Unit-II (ATU-II)............................................................ 173

10.1

Overview............................................................................................................................ 173

10.1.1 Features ................................................................................................................ 173

10.1.2 Pin Configuration ................................................................................................. 178

10.1.3 Register Configuration ......................................................................................... 182

10.1.4 Block Diagrams.................................................................................................... 192

10.1.5 Inter-Channel and Inter-Module Signal Communication Diagram...................... 202

10.1.6 Prescaler Diagram ................................................................................................ 203

10.2

Register Descriptions......................................................................................................... 204

10.2.1 Timer Start Registers (TSTR) .............................................................................. 204

10.2.2 Prescaler Registers (PSCR) .................................................................................. 208

10.2.3 Timer Control Registers (TCR)............................................................................ 209

10.2.4 Timer I/O Control Registers (TIOR).................................................................... 219

10.2.5 Timer Status Registers (TSR) .............................................................................. 231

10.2.6 Timer Interrupt Enable Registers (TIER)............................................................. 260

10.2.7 Interval Interrupt Request Registers (ITVRR) ..................................................... 282

10.2.8 Trigger Mode Register (TRGMDR) .................................................................... 286

10.2.9 Timer Mode Register (TMDR) ............................................................................ 286

10.2.10 PWM Mode Register (PMDR) ............................................................................. 288

10.2.11 Down-Count Start Register (DSTR) .................................................................... 290

10.2.12 Timer Connection Register (TCNR) .................................................................... 296

10.2.13 One-Shot Pulse Terminate Register (OTR).......................................................... 301

10.2.14 Reload Enable Register (RLDENR) .................................................................... 305

10.2.15 Free-Running Counters (TCNT) .......................................................................... 306

10.2.16 Down-Counters (DCNT)...................................................................................... 308

10.2.17 Event Counters (ECNT) ....................................................................................... 309

10.2.18 Output Compare Registers (OCR)........................................................................ 310

10.2.19 Input Capture Registers (ICR).............................................................................. 311

10.2.20 General Registers (GR) ........................................................................................ 312

10.2.21 Offset Base Registers (OSBR) ............................................................................. 314

10.2.22 Cycle Registers (CYLR) ...................................................................................... 315

10.2.23 Buffer Registers (BFR) ........................................................................................ 316

10.2.24 Duty Registers (DTR) .......................................................................................... 317

10.2.25 Reload Register (RLDR) ...................................................................................... 318

10.2.26 Channel 10 Registers............................................................................................ 318

10.3

Operation ........................................................................................................................... 333

10.3.1 Overview .............................................................................................................. 333

10.3.2 Free-Running Counter Operation and Cyclic Counter Operation........................ 339

10.3.3 Compare-Match Function .................................................................................... 341

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