SH-2 datasheet(82/919 Pages) RENESAS

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4.1.2

Pin Configuration

The pins relating to the clock pulse generator are shown in table 4.1.

Table 4.1

CPG Pins

Pin Name

Abbreviation

I/O

Description

External clock

EXTAL

Input

Crystal resonator or external clock input

Crystal

XTAL

Input

Crystal resonator connection

System clock

Output

System clock output

PLL power supply

PLLV

Input

PLL multiplier circuit power supply

PLL ground

PLLV

Input

PLL multiplier circuit ground

PLL capacitance

PLLCAP

Input

PLL multiplier circuit oscillation external

capacitance pin

4.2

Frequency Ranges

The input frequency and operating frequency ranges are shown in table 4.2.

Table 4.2

Input Frequency and Operating Frequency

Input Frequency Range

(MHz)

PLL Multiplication Factor

Operating Frequency Range

(MHz)

5 to 10

×4

20 to 40

Note:

Crystal resonator and external clock input

For the chip operating frequency, a frequency of 4 times the input frequency (EXTAL pin) is

generated as the internal clock (

φ) by the on-chip PLL circuit. The system clock (CK pin) output

frequency is the same as that of the internal clock (

φ).

Some on-chip peripheral modules operate on a peripheral clock (P

φ) obtained by dividing the

internal clock (

φ) by 2. Figure 4.2 shows the relationship between the various clocks. As regards

the system clock, since the input clock is multiplied by the PLL multiplier circuit, the phases of

both clocks are not determined uniformly.

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