SH-2 datasheet(87/919 Pages) RENESAS

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Section 5 Exception Processing

5.1

Overview

5.1.1

Types of Exception Processing and Priority

Exception processing is started by four sources: resets, address errors, interrupts and instructions

and have the priority shown in table 5.1. When several exception processing sources occur at once,

they are processed according to the priority shown.

Table 5.1

Types of Exception Processing and Priority Order

Exception

Source

Priority

Reset

Power-on reset

High

Manual reset

Address

CPU address error

error

DMAC address error

Interrupt

NMI

User break

IRQ

On-chip peripheral modules:

• Direct memory access controller (DMAC)

• Advanced timer unit-II (ATU-II)

• Compare match timer 0 (CMT0)

• A/D converter channel 0 (A/D0)

• Compare match timer (CMT1)

• A/D converter channel 1 (A/D1)

• Serial communication interface (SCI)

• Hitachi controller area network (HCAN)

• Watchdog timer (WDT)

Instructions Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Illegal slot instructions (undefined code placed directly after a delay branch

instruction*

1 or instructions that rewrite the PC*2)

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF.

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