SH-2 datasheet(7/919 Pages) RENESAS

7 / 919 page

Main Revisions and Additions in this Edition

Page

Item

Revisions (See Manual for Details)

1.3.1 Pin Arrangement

Name of 155 th pin amended (PK11/TO8L)

5.1.1 Types of Exception

Processing and Priority

Table 5.1 Types of Exception Processing and Priority

Order

Compare match timer (CMT1), A/D converter channel 1

(A/D1) added

Module abbreviations amended: CMT0, A/D0

160

9.3.5 Dual Address Mode

Figure 9.5 Dual Address Mode and Indirect Address

Operation (16-Bit-Width External Memory Space)

Description of 1st and 2nd bus cycles amended

If the data bus is 16 bits wide when the external

memory space is accessed, two bus cycles are

necessary.

217

10.2.3 Timer Control Registers

(TCR)

Timer Control Register 9A, 9B, 9C (TCR9A, TCR9B,

TCR9C) Description of Bits 1 and 0 amended

x=A, C, or E

306

10.2.15 Free-Running Counters

(TCNT)

Description of Free-Running Counter 0 added

When the bits corresponding to the timer start register 1

(TSTR1) are set to 1, this counter starts to count.

307

Description of Free-Running Counters 1A, 1B, 2A, 2B,

3, 4, 5, 11 added

When the bits corresponding to the timer start register

1, 3 (TSTR1, TSTR3) are set to 1, these counters start

to count.

335

10.3.1 Overview

Description of Channel 2 amended

337

Description of Channel 10 amended

348

10.3.9 PWM Timer Function

Description amended

..., and H'0002, H'0003, H'0004 (100%), and H'0000

(0%) in BFR6A.

375

10.6 Sample Setup Procedures Sample Setup Procedure for Channel 0 Input Capture

Triggered by Channel 10 Compare-Match

399

Writing to ROM Area

Immediately after ATU Register

Write

Description added

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