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SH7101 датащи(PDF) 31 Page - Renesas Technology Corp |
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SH7101 датащи(HTML) 31 Page - Renesas Technology Corp |
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31 / 560 page ![]() Rev.1.00 Sep. 18, 2008 Page xxxi of xxxiv REJ09B0069-0100 Table 8.21 TIORL_3 (Channel 3) ............................................................................................ 140 Table 8.22 TIORH_4 (Channel 4)............................................................................................ 141 Table 8.23 TIORH_4 (Channel 4)............................................................................................ 142 Table 8.24 TIORL_4 (Channel 4) ............................................................................................ 143 Table 8.25 TIORL_4 (Channel 4) ............................................................................................ 144 Table 8.26 Output Level Select Function................................................................................. 154 Table 8.27 Output Level Select Function................................................................................. 155 Table 8.28 Output Level Select Function................................................................................. 157 Table 8.29 Register Combinations in Buffer Operation........................................................... 165 Table 8.30 Cascaded Combinations ......................................................................................... 168 Table 8.31 PWM Output Registers and Output Pins................................................................ 171 Table 8.32 Phase Counting Mode Clock Input Pins................................................................. 175 Table 8.33 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 176 Table 8.34 Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 177 Table 8.35 Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 178 Table 8.36 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 179 Table 8.37 Output Pins for Reset-Synchronized PWM Mode.................................................. 181 Table 8.38 Register Settings for Reset-Synchronized PWM Mode ......................................... 181 Table 8.39 Output Pins for Complementary PWM Mode ........................................................ 185 Table 8.40 Register Settings for Complementary PWM Mode................................................ 186 Table 8.41 Registers and Counters Requiring Initialization..................................................... 193 Table 8.42 MTU Interrupts ...................................................................................................... 210 Table 8.43 Mode Transition Combinations .............................................................................. 234 Table 8.44 Pin Configuration ................................................................................................... 263 Table 8.45 Pin Combinations ................................................................................................... 263 Section 9 Watchdog Timer Table 9.1 Pin Configuration ................................................................................................... 272 Table 9.2 WDT Interrupt Source (in Interval Timer Mode)................................................... 279 Section 10 Serial Communication Interface (SCI) Table 10.1 Pin Configuration ................................................................................................... 285 Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0..................... 293 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 294 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 294 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. 295 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. 295 Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode)............................................................................................ 296 Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................. 297 |
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