SH7101 datasheet(30/560 Pages) RENESAS

30 / 560 page

Rev.1.00 Sep. 18, 2008 Page xxx of xxxiv

REJ09B0069-0100

Table 5.5

Reset Status ............................................................................................................

Table 5.6

Bus Cycles and Address Errors ..............................................................................

Table 5.7

Interrupt Sources ....................................................................................................

Table 5.8

Interrupt Priority.....................................................................................................

Table 5.9

Types of Exceptions Triggered by Instructions......................................................

Table 5.10

Generation of Exception Sources Immediately after a Delayed Branch

Instruction or Interrupt-Disabled Instruction..........................................................

Table 5.11

Stack Status after Exception Processing Ends........................................................

Section 6 Interrupt Controller (INTC)

Table 6.1

Pin Configuration ...................................................................................................

Table 6.2

Interrupt Exception Processing Vectors and Priorities...........................................

Table 6.3

Interrupt Response Time ........................................................................................

Section 7 Bus State Controller (BSC)

Table 7.1

Pin Configuration ...................................................................................................

Table 7.2

Address Map ..........................................................................................................

Table 7.3

Access to Internal I/O Registers ............................................................................. 113

Section 8 Multifunction Timer Pulse Unit (MTU)

Table 8.1

MTU Functions ...................................................................................................... 116

Table 8.2

Pin Configuration ................................................................................................... 119

Table 8.3

CCLR0 to CCLR2 (Channels 0, 3, and 4).............................................................. 123

Table 8.4

CCLR0 to CCLR2 (Channels 1 and 2)................................................................... 123

Table 8.5

TPSC0 to TPSC2 (Channel 0)................................................................................ 124

Table 8.6

TPSC0 to TPSC2 (Channel 1)................................................................................ 124

Table 8.7

TPSC0 to TPSC2 (Channel 2)................................................................................ 125

Table 8.8

TPSC0 to TPSC2 (Channels 3 and 4)..................................................................... 125

Table 8.9

MD0 to MD3.......................................................................................................... 127

Table 8.10

TIORH_0 (Channel 0)............................................................................................ 129

Table 8.11

TIORH_0 (Channel 0)............................................................................................ 130

Table 8.12

TIORL_0 (Channel 0) ............................................................................................ 131

Table 8.13

TIORL_0 (Channel 0) ............................................................................................ 132

Table 8.14

TIOR_1 (Channel 1)............................................................................................... 133

Table 8.15

TIOR_1 (Channel 1)............................................................................................... 134

Table 8.16

TIOR_2 (Channel 2)............................................................................................... 135

Table 8.17

TIOR_2 (channel 2) ............................................................................................... 136

Table 8.18

TIORH_3 (Channel 3)............................................................................................ 137

Table 8.19

TIORH_3 (Channel 3)............................................................................................ 138

Table 8.20

TIORL_3 (Channel 3) ............................................................................................ 139

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