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H8S2245 датащи(PDF) 397 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 397 Page - Renesas Technology Corp |
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397 / 818 page ![]() Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 355 of 772 REJ09B0355-0300 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is prohibited. A compare match does not occur even if the same value as before is written. Figure 9.47 shows the timing in this case. Compare match signal Write signal Address φ TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N+1 Prohibited Figure 9.47 Contention between TGR Write and Compare Match |
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