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H8S2245 датащи(PDF) 393 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 393 Page - Renesas Technology Corp |
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393 / 818 page ![]() Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 351 of 772 REJ09B0355-0300 Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by the CPU, and figure 9.43 shows the timing for status flag clearing by the DTC. Status flag Write signal Address φ TSR address Interrupt request signal TSR write cycle T1 T2 Figure 9.42 Timing for Status Flag Clearing by CPU Interrupt request signal Status flag Address φ Source address DTC read cycle T1 T2 Destination address T1 T2 DTC write cycle Figure 9.43 Timing for Status Flag Clearing by DTC Activation |
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