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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 338 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 338 Page - Renesas Technology Corp |
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338 / 818 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 296 of 772 REJ09B0355-0300 9.2.2 Timer Mode Register (TMDR) 7 — 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 0 MD0 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W Bit Initial value R/W : : : Channel 0: TMDR0 7 — 1 — 6 — 1 — 5 — 0 — 4 — 0 — 3 MD3 0 R/W 0 MD0 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W Bit Initial value R/W : : : Channel 1: TMDR1 Channel 2: TMDR2 The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TCNT operation should be stopped when making TMDR settings. Bits 7 and 6—Reserved: Read-only bits, always read as 1. Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB Description 0 TGRB operates normally (Initial value) 1 TGRB and TGRD used together for buffer operation |
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