M32CSLASH8A datasheet(269/372 Pages) RENESAS

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M32C/8A Group

18. A/D Converter

Rev.1.00

Jul 15, 2007

Page 252 of 352

REJ09B0385-0100

Table 18.1

A/D Converter Specifications

NOTES:

1. The

φAD frequency must be16 MHz or lower when VCC1 = 4.2 to 5.5 V.

The

φAD frequency must be10 MHz or lower when VCC1 = 3.0 to 5.5 V.

Without the sample and hold function, the

φAD frequency must be 250 kHz or higher.

With the sample and hold function, the

φAD frequency must be 1 MHz or higher.

2. AVCC = VCC1

AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1)

≤ VCC1

Item

Specification

A/D conversion method

Successive approximation (with capacitance coupled amplifier)

Analog input voltage

0 V to AVCC (VCC1)

Operating clock

φAD(1)

fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8

Resolution

Selectable from 8 bits or 10 bits

Operating modes

• One-shot mode

• Repeat mode

• Single sweep mode

• Repeat sweep mode 0

• Repeat sweep mode 1

• Multi-port single sweep mode

• Multi-port repeat sweep mode 0

Analog input pins(2)

144 pin package: 18 pins

8 pins each for AN (AN_0 to AN_7), AN15 (AN15_0 to AN15_7)

2 extended input pins (ANEX0 and ANEX1)

100 pin package: 10 pins

8 pins for AN (AN_0 to AN_7)

2 extended input pins (ANEX0 and ANEX1)

A/D conversion start condition

• Software trigger

The ADST bit in the AD0CON0 register is set to “1” (A/D conversion starts).

• External trigger (retrigger is enabled)

When the falling edge is detected at the ADTRG pin after the ADST bit is set to 1.

• Hardware trigger (retrigger is enabled)

Timer B2 interrupt request of the three-phase motor control timer function (after

the ICTB2 register completes counting) is generated after the ADST bit is set

to 1.

Conversion rate per pin

• Without sample and hold function

8-bit resolution: 49

φAD cycles, 10-bit resolution: 59 φAD cycles

• With sample and hold function

8-bit resolution: 28

φAD cycles, 10-bit resolution: 33 φAD cycles

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