M32CSLASH8A datasheet(204/372 Pages) RENESAS

204 / 372 page

M32C/8A Group

16. Three-Phase Motor Control Timer Function

Rev.1.00

Jul 15, 2007

Page 187 of 352

REJ09B0385-0100

Figure 16.9

TA1, TA2, TA4, TA11, TA21, and TA41 Registers, IDB0, IDB1 Registers

Symbol

TA1, TA2, TA4

TA11, TA21, TA41

Address

0349h - 0348h, 034Bh - 034Ah, 034Fh - 034Eh

0303h - 0302h, 0305h - 0304h, 0307h - 0306h

After Reset

Undefined

Function

Timer Ai, Ai1 Register(1, 2, 3, 4, 5) (i = 1, 2, 4)

If a setting value is n, f1 is counted n times after a start trigger

occurs, and then the timer stops. Output signal level for each

phase changes when timers A1, A2, or A4 stop.

NOTES:

1. Write these registers in 16-bit units. Read-modify-write instructions cannot be used to set registers TAi and TAi1. Refer to

Usage Notes for details.

2. If the TAi or TAi1 register is set to 0000h, the counter does not start and the timer Ai interrupt is not generated.

3. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled), an output signal is switched to its active level with

delay simultaneously with the dead time timer underflow.

4. When the INV11 bit is set to 0 (Timers A11, A21, and A41 are not used (three-phase mode 0)), the contents of the TAi register

are transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to 1 (Timers A11, A21, and A41 are

used (three-phase mode 1)), the contents of the TAi1 register are transferred by the first timer Ai start trigger, and then contents

of the TAi register are transferred by the next timer Ai start trigger. Subsequently, the contents of registers TAi1 and TAi are

transferred alternately to the reload register by each timer Ai start trigger.

5. Do not set registers TAi and TAi1 in the timer B2 underflow timing.

Setting Range

0000h to FFFFh

b15

Three-Phase Output Buffer Register i(1) (i = 0, 1)

Symbol

IDB0, IDB1

Address

030Ah, 030Bh

Bit Symbol

DUi

After Reset

XX11 1111b

NOTE:

1. When values are written to registers IDB0 and IDB1, these values are transferred to the three-phase output shift registers by a

transfer trigger. The value written in the IDB0 register becomes the initial output level of each phase when the transfer trigger occurs.

The value written in the IDB1 register becomes the next output signal level when the falling edge of the timer A1, A2 and A4 one-shot

pulses is detected.

DUBi

DVi

DVBi

DWi

DWBi

−

(b7-b6)

−

b7 b6 b5 b4

Bit Name

Upper arm (U-phase)

output buffer i

Upper arm (V-phase)

output buffer i

Lower arm (V-phase)

output buffer i

Upper arm (W-phase)

output buffer i

Function

Set output levels of the three-phase output shift

registers. The set value is reflected in each

turn-on signal as follows:

0: Active (ON)

1: Inactive (OFF)

When read, the contents of the three-phase

output shift registers are returned.

Unimplemented.

Write 0. Read as undefined value.

Lower arm (U-phase)

output buffer i

Lower arm (W-phase)

output buffer i

M32C/8A датащи(PDF) 204 Page - Renesas Technology Corp

M32C/8A датащи(HTML) 204 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL