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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/8A датащи(PDF) 174 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 174 Page - Renesas Technology Corp |
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174 / 372 page  M32C/8A Group 15. Timers (Timer A) Rev.1.00 Jul 15, 2007 Page 157 of 352 REJ09B0385-0100 Figure 15.15 Operation in Event Counter Mode When Not Handling Two-Phase Pulse Signals Count starts FFFFh n Count stops i = 0 to 4 TAiS bit in the TABSR register Contents of the counter n = contents of the reload register 0000h IR bit in the TAiIC register 0 1 Input to TAiIN pin (Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode) The MR1 bit is set to 1 (rising edges of an external signal counted) The MR2 bit is set to 0 (UDF register setting) Bits TCK1 to TCK0 bit are set to 00b (reload) Underflow Reload Overflow Reload 0 1 “L” “H” Set to 0 by an interrupt request acknowledgement or by program Decrement to increment Count resumes TAiUD bit in the UDF register 0 1 Set to 1 by program |
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