M32CSLASH8A datasheet(165/372 Pages) RENESAS

165 / 372 page

M32C/8A Group

15. Timers (Timer A)

Rev.1.00

Jul 15, 2007

Page 148 of 352

REJ09B0385-0100

Figure 15.8

TA0MR to TA4MR Registers in Pulse Width Modulation Mode

b7 b6

0 0: f1

0 1: f8

1 0: f2n (2)

1 1: fC32

Set to 0

b6 b5 b4

Symbol

TA0MR to TA4MR

Address

0356h, 0357h, 0358h, 0359h, 035Ah

After Reset

00h

Function

Bit Symbol

Bit Name

MR3

TCK1

MR2

MR1

Count source select bits

TCK0

Timer Ai Mode Register (i = 0 to 4)(Pulse Width Modulation Mode)

TMOD1

Reserved bit

−

(b2)

b1 b0

1 1: Pulse width modulation (PWM) mode

Operating mode select bits

TMOD0

0: Falling edge of signal applied to the TAiIN pin

1: Rising edge of signal applied to the TAiIN pin

External trigger select bit(1)

0: The TAiS bit is enabled

1: Selected by bits TAiTGH and TAiTGL

Trigger select bit

0: Functions as 16-bit pulse width modulator

1: Functions as 8-bit pulse width modulator

16/8-bit PWM mode select bit

NOTES:

1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN

pin).

The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj

(j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow).

2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the

CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.

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