M32CSLASH8A datasheet(147/372 Pages) RENESAS

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M32C/8A Group

13. DMAC

Rev.1.00

Jul 15, 2007

Page 130 of 352

REJ09B0385-0100

13.1

Transfer Cycles

The transfer cycle is composed of bus cycles to read data from source address (source read) and bus cycles to write

data to destination address (destination write). The number of read and write bus cycles depends on the locations

of source and destination addresses. In microprocessor mode, the number of read and write bus cycles also depends

on DS register setting. Software wait state insertion and the RDY signal can extend a bus cycle.

13.1.1

Effect of Source and Destination Addresses

When a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, the

source-read cycle is added by one bus cycle, compared to a source address starting with an even address.

When a 16-bit data is transferred with a 16-bit data bus and a destination address starts with an odd address, the

destination-write cycle is added by one bus cycle, compared to a destination address starting with an even

address.

13.1.2

Effect of the DS Register

In an external space in microprocessor mode, the transfer cycle varies depending on the data bus width of the

source and destination addresses. See Figure 8.1 for details about the DS register.

• When a 16-bit data is transferred accessing both source address and destination address with an 8-bit data

bus (the DSi bit in the DS register is set to 0 (i = 0 to 3)), an 8-bit data will be transferred twice. Therefore,

two bus cycles are required for reading and another two bus cycles for writing.

• When a 16-bit data is transferred accessing a source address with an 8-bit data bus (the DSi bit is set to 0)

and a destination address with a 16-bit data bus, an 8-bit data will be read twice but be written once as 16-

bit data. Therefore, two bus cycles are required for reading and one bus cycle for writing.

• When a 16-bit data is transferred accessing a source address with a 16-bit data bus (the DSi bit is set to 1)

and a destination address with an 8-bit data bus, a 16-bit data will be read once and an 8-bit data will be

written twice. Therefore, one bus cycle is required for reading and two bus cycles for writing.

13.1.3

Effect of Software Wait State

When accessing the SFR area or memory space that require wait states, the number of bus clocks (BCLK) is

increased by software wait states.

13.1.4

Effect of the RDY Signal

In microprocessor mode, the RDY signal affects a bus cycle if a source address or destination address is in an

external space. Refer to 8.2.6 RDY Signal for details.

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