M32CSLASH8A datasheet(116/372 Pages) RENESAS

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M32C/8A Group

11. Interrupts

Rev.1.00

Jul 15, 2007

Page 99 of 352

REJ09B0385-0100

11.5

Interrupts and Interrupt Vectors

There are four bytes in each interrupt vector. Set the starting address of an interrupt routine in each interrupt vector.

When an interrupt request is acknowledged, an interrupt routine is executed from the address set in its interrupt

vector. Figure 11.3 shows an interrupt vector.

Figure 11.3

Interrupt Vector

11.5.1

Fixed Vector Table

The fixed vector table is allocated addresses FFFFDCh to FFFFFFh. Table 11.1 lists the fixed vector table.

Table 11.1

Fixed Vector Table

11.5.2

Relocatable Vector Table

The relocatable vector table occupies 256 bytes beginning from the address set in the INTB register. Tables

11.2 and 11.3 list the relocatable vector table.

Set an even address to the starting address of the vector set in the INTB register to increase the interrupt

sequence execution rate.

Interrupt

Source

Vector Addresses

Address (L) to Address (H)

Remarks

Reference

Undefined

instruction

FFFFDCh to FFFFDFh

M32C/80 series

software manual

Overflow

FFFFE0h to FFFFE3h

BRK instruction

FFFFE4h to FFFFE7h

If the content of the address

FFFFE7h is FFh, the CPU

executes from the address

stored into software interrupt

number 0 in the relocatable

vector table.

Address match

FFFFE8h to FFFFEBh

−

FFFFECh to FFFFEFh

Reserved space

Watchdog timer

FFFFF0h to FFFFF3h

These addresses are used for

the watchdog timer interrupt,

oscillation stop detection

interrupt, and Vdet4 detection

interrupt.

Reset,

clock generation circuit,

watchdog timer

−

FFFFF4h to FFFFF7h

Reserved space

NMI

FFFFF8h to FFFFFBh

Reset

FFFFFCh to FFFFFFh

Reset

8 Middle-order bits of address

8 Low-order bits of address

00h

Vector address+0

LSB

MSB

Vector address+1

Vector address+2

Vector address+3

8 High-order bits of address

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