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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 281 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 281 Page - Renesas Technology Corp |
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281 / 646 page  Section 11 Ethernet Controller (EtherC) Rev. 6.00 Jun. 12, 2007 Page 249 of 610 REJ09B0131-0600 3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting. 11.4.2 Reception The EtherC receiver separates the frame data (MII into preamble, SFD, DA (destination address), SA (Source address), type/length, Data, and CRC data) and outputs DA, SA, type/length, Data to the E-DMAC. Figure 11.3 shows the state transitions of the EtherC receiver. Illegal carrier detection Start of frame reception Wait for SFD reception Data reception CRC reception Destination address reception Preamble detection Reception halted Reset Error notification* RE set [Legend] SFD: Start frame delimiter Note: * The error frame also transmits data to the buffer. End of reception Receive error detection Receive error detection Error detection Promiscuous and other station destination address RE reset Normal reception Idle RX-DV negation SFD reception Own destination address or broadcast or multicast or promiscuous Figure 11.3 EtherC Receiver State Transmissions |
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