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R8C датащи(PDF) 103 Page - Renesas Technology Corp |
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R8C датащи(HTML) 103 Page - Renesas Technology Corp |
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103 / 199 page ![]() R8C/10 Group 13. Serial Interface Rev.1.20 Jan 27, 2006 page 93 of 180 REJ09B0019-0120 UARTi transmit/receive control register 1 (i=0, 1) SymbolAddressAfter reset U0C100A516 0216 U1C100AD16 0216 b7b6b5b4b3b2b1b0 Bit name Bit symbol RW Function TE TI RE RI Transmit enable bit Receive enable bit(1) Receive complete flag(2) Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register Nothing is assigned. When write, set “0”. When read, its content is “0”. RW RW RO RO (b7-b4) NOTES: 1. As for the UART1, set the TXD1EN bit in the UCON register before setting this bit to reception enabled. 2. The RI bit is set to "0" when the higher byte of the UiRB register is read. Figure 13.5 U0C1 and U1C1 Registers and UCON Register NOTES: 1. For P37, select “0” (RxD1) for data receive, and “1” (TxD10) for data transfer. Set the PD3_7 bit in the PD3 register to “0” (input mode) when receiving. 2. Do not set the TXD1SEL and TXD1EN bits to “1” at the same time since they function independently. UART transmit/receive control register 2 SymbolAddressAfter reset UCON00B016 0016 b7b6b5 b4b3b2b1b0 Bit name Bit symbol RW Function TXD1SEL TXD1EN UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Port TxD11 switching bit(2) UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : RxD1 1 : TxD10 Nothing is assigned. When write, set “0”. When read, its content is “0”. U0IRS U1IRS U0RRM TxD10/RxD1 select bit(2) 0 : I/O port P00 1 : TxD11 Must set to “0” RW RW RW RW RW RW (b7) (b4-b3) Reserved bit 0 0 |
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