R8C datasheet(83/199 Pages) RENESAS

83 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 73 of 180

REJ09B0019-0120

TZSC register

Timer Y underflow

Toggle flip-flop

P3_1 bit in P3 register

TZOUT

Data bus

Reload register

TZPR register

Counter

PREZ register

Input polarity selected to be

one edge or both edges

Digital

filter

Polarity

select

INT0

TZS

TZOS

INOSEG

TZOCNT=0

INT0PL

TZMOD1 to TZMOD0=012, 102, 112

INT0EN

TZOCNT=1

TZOPL=0

TZOPL=1

TZMOD1 to TZMOD0=102

, 112

TZCK1 to TZCK0

=002

=012

=102

=112

Timer Z interrupt

INT0 interrupt

CLR

Write to TYZMR register

TZMOD1 to TZMOD0 bits=012, 102, 112

Figure 12.19 TYZMR Register

12.3 Timer Z

Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer

Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR,

PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers.

Timer Z has the following four operation modes.

• Timer mode: The timer counts an internal count source or Timer Y underflow.

• Programmable waveform generation mode: The timer outputs pulses of a given width successively.

• Programmable one-shot generation mode: The timer outputs one-shot pulse.

• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.

Timer Y, Z mode register

SymbolAddressAfter reset

TYZMR008016

0016

Bit name

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Timer mode

0 1 : Programmable waveform generation mode

1 0 : Programmable one-shot generation mode

1 1 : Programmable wait one-shot generation

mode

TZMOD1

TYS

TYWC

TYMOD0

TZMOD0

Timer Y operation

mode bit

Timer Y write

control bit

Function varies depending on the operation

mode

0 : Timer mode

1 : Programmable waveform generation mode

TZWC

TZS

0 : Stops counting

1 : Starts counting

0 : Stops counting

1 : Starts counting

Timer Z count

start flag

Timer Z operation

mode bit

b5 b4

Timer Y count

start flag

Timer Z write

control bit

Function varies depending on the operation

mode

R1EDG

0 : Rising edge

1 : Falling edge

INT2/CNTR1 polarity

switching bit(1)

NOTES:

1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.

Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.

Figure 12.18 Timer Z Block Diagram

12.3 Timer (Timer Z)

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