STV0118 datasheet(5/42 Pages) STMICROELECTRONICS

5 / 42 page

II - PIN INFORMATION (continued)

Name

Type

Function

CKREF

Master clock reference signal.

Its rising edge is the default reference for set-up and hold times of all inputs, and for

propagation delay of all outputs (except for SDA output).

CKREF nominal frequency is 27MHz (CCIR601) : input pad with pull down (50k

Ω Typ.)

RESET

Hardware reset, active LOW.

It has priority over software reset. NRESET imposes default states (see Register Contents).

Minimum Low level required duration is 5 CKREF periods : input pad with pull down

(50k

Ω Typ.)

SCL

2C bus clock line (internal 5-bit majority logic with CKREF for reference) : input pad with

pull down (50k

Ω Typ.)

SDA

I/O

2C bus serial data line.

Input : internal 5-bit majority logic with CKREF for reference

Output : open drain

VSYNC/

ODDEVEN

I/O

Frame sync signal :

- input in slave modes, except when sync is extracted from YCrCb data

- output in master mode and when sync is extracted from YCrCb data

- synchronous to rising edge of CKREF

- ODDEVEN default polarity :

odd (not-top) field : LOW level

even (bottom) field : HIGH level

II.2 - Pin Description (continued)

III - BLOCK DIAGRAM

SSA

DDA

CTRL + CFG

LUMA

PROCESSING

CLOSED

CAPTIONS

CGMS

CHROMA

PROCESSOR

TRAP

RGB ENCODING

CB-CR

SYNC CONTROL

& VIDEO TIMING

GENERATOR

YCRCB7

RE F(CVBS)

VR_CVBS

CVBS

REF(RGB)

VR_RGB

B/CVBS

SSA

DDA

G/Y

R/C

TTXD

9-BIT

DAC

TELETEXT

YCRCB6

YCRCB5

YCRCB4

YCRCB3

YCRCB2

YCRCB1

YCRCB0

CSI2C

TTXS

STV0118

SDA

SCL

I2C BUS

CSI2C

VSYNC/ODDEVEN

HSYNC

RESET

CKREF

TTXS/

CSI2C

SSA

DDA

AUTOTEST

COLOR BAR

PATTERN

STV0118

5/42

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