STV0118 datasheet(12/42 Pages) STMICROELECTRONICS

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HSYNC

(in)

ODDEVEN

(in)

CKREF

YCRCB

Y’

Active Edge (programmable polarity)

Note :

1. This figure is valid for bits “syncin_ad[1:0]” = default.

Figure 11 : HSYNC + ODDEVEN Based Slave Mode Sync Signals

IV - FUNCTIONAL DESCRIPTION (continued)

IV.5 - Slave Modes

Six slave modes are available : ODDEV+HSYNC

based (line-based sync), VSYNC+HSYNC based

(another type of line-based sync), ODDEV-only

based (frame-based sync), VSYNC-only based

(another type of frame-based sync), or sync-in-

data based (line locked or frame locked).

ODDEV refers to an odd/even (also known as

not-top/bottom) field flag, HSYNC is a line sync

signal, VSYNCis a vertical sync signal. Their wave-

forms are depicted in Figure 9. The polarities of

HSYNC and VSYNC/ODDEV are independently

programmable in all slave modes.

IV.5.1- Synchronization onto a Line Sync Signal

IV.5.1.1- HSYNC+ODDEV Based Synchronization

Synchronization is performed on a line-by-line ba-

sis by locking onto incoming ODDEV and HSYNC

signals. Refer to Figure 11 for waveforms and

timings. The polarities of the active edges of

HSYNC and ODDEV are programmable and inde-

pendent.

The first active edge of ODDEV initializes the inter-

nal line counter but encoding of the first line does

not start until an HSYNC active edge is detected

(at the earliest, HSYNC may transition at the same

time as ODDEV). At that point, the internal sample

counter is initialized and encoding of the first line

starts. Then, encoding of each subsequent line is

individually triggered by HSYNC active edges. The

phase relationship between HSYNC and the in-

coming YCrCB data is normally such that the first

clock rising edge following the HSYNC active edge

samples “Cb” (i.e. a ‘blue’ chroma sample within

the YCrCb stream). It is however possible to inter-

na l l y del ay t h e inc omi ng s y n c s i g na l s

(HSYNC+ODDEV) by up to 3 clock cycles to cope

with different data/sync phasings, using configura-

tion bits “Syncin_ad” (Reg. 4).

The STV0118 is thus fully slaved to the HSYNC

signal, which means that lines may contain more

or less samples than typical 525/625 system re-

quirement.

If the digital line is shorter than its nominal value:

the sample counter is re-initialized when the ‘early’

HSYNC arrives and all internal synchronization

signals are re-initialized.

If the digital line is longer than its nominal value :

the sample counter is stopped when it reaches its

nominal end-of-line value and waits for the ‘late’

HSYNC before reinitializing.

The field counter is incremented on each ODDEV

transition. The line counter is reset on the HSYNC

following each active edge of ODDEV.

IV.5.1.2- HSYNC+VSYNC Based Synchronization

Synchronization is performed on a line-by-line ba-

sis by locking onto incoming VSYNC and HSYNC

signals. Refer to Figure 12 for waveforms and

timings. The polarities of HSYNC and VSYNC are

programmable and independent.

The incoming VSYNC signal is immediately trans-

formed into a waveform identical to the odd/even

waveform of an ODDEV signal, therefore the be-

havior of the core is identical to that described

above for ODDEV+HSYNC based synchroniza-

tion. Again, the phase relationship between

HSYNC and the incoming YCrCb data is normally

such that the first clock rising edge following the

HSYNC active edge samples “Cb” (i.e. a ‘blue’

chroma sample within the YCrCb stream). It is

however possible to internally delay the incoming

sync signals (HSYNC+VSYNC) by up to 3 clock

cycles to cope with different data/sync phasings,

using configuration bits “Syncin_ad” (Reg. 4).

The field counter is incremented on each active

edge of VSYNC.

STV0118

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