STV0118 datasheet(34/42 Pages) STMICROELECTRONICS

34 / 42 page

VI.2 - Register Contents and Description (continued)

(*) = DEFAULT mode when NRESET pin is active (LOW level)

VI - REGISTERS (continued)

REGISTER_6 - Configuration6

MSB

LSB

Content

softreset

jump

dec_ninc

free_jump

xxxx

chgi2c

maxdyn

Default

010

softreset

Software reset

(*)

No reset

Software reset

Note :

Bit ‘softreset’ is automatically reset after internal reset generation.

Software reset is active during 4 CKREF periods. When softreset is activated, all the device is reset as with

hardware reset except for the first six user registers (configurations) and for registers 10 up to 14

(increment and phase of oscillator), 31-33, 34-37 and 39-42.

jump, dec_ninc, free_jump

jump dec_ninc free_jump

Normal mode (no line skip/insert capability)

CCIR : 313/312 or 263/262

non-interlaced : 312/312 or 262/262

Manual mode for line insert (“dec_ninc” = 0) or skip

(“dec_ninc” = 1) capability.

Both fields of all the frames following the I

2C writing are

modified accordingto “lref”and “ltarg” bits of registers21-22-23

(by default, “lref” = 0 and “ltarg” = 1 which leads to normal mode

above).

Automatic line insert mode.

The 2

nd field of the frame following the I2C writing is increased.

Line insertion is done after line 245 in 525/60 and after line 330

in 625/50. “lref” and “ltarg” bits are ignored.

Automatic line skip mode.

The 2

nd field of the framefollowing the I2C writtingis decreased.

Line suppression is done after line 245 in 525/60 and after

line 330 in 625/50. “lref” and “ltarg” bits are ignored.

Not be used

Notes :

- Refer to Functional Description (Section IV.18)

- bit “jump” is automatically reset after use.

chgi2c

Chip address selection

(*)

Chip address : write = 40hex ; read = 41hex

Chip address : write = 42hex; read = 43hex

Note :

Setting this bit to 1 changes the chip address provided that pin ttxs/csi2c is tied to Vdd when the 0-to-1

transition occurs. Refer to sections IV.16 and IV.17. The new address is valid until the next hardware reset.

maxdyn

Max dynamic magnitude allowed on YCrCb inputs for encoding

(Refer to Functional Description, Section IV.6).

(*)

10hex to EBhex for Y, 10hex to E0hex for chrominance (Cr,Cb)

01hex to FEhex for Y, Cr and Cb

Note :

In any case, EAV and SAV words are replaced by blanking values before being fed to the luminance and

chrominace processings

REGISTER_7 and 8 : Reserved

STV0118

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