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4501 датащи(PDF) 13 Page - Renesas Technology Corp

номер детали 4501
подробное описание детали  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  116 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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4501 датащи(HTML) 13 Page - Renesas Technology Corp

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4501 Group
Rev.3.01
2005.02.07
page 13 of 112
REJ03B0104-0301
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-
bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, ex-
change, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Fig-
ure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
Register D is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
Fig. 1 AMC instruction execution example
Fig. 2 RAR instruction execution example
Fig. 3 Registers A, B and register E
Fig. 4 TABP p instruction execution example
(CY)
(M(DP))
(A)
Addition
ALU
<Carry>
<Result>
A3 A2 A1 A0
B3 B2 B1 B0
E7 E6 E5 E4 E3 E2 E1 E0
A3 A2 A1 A0
B3 B2 B1 B0
TAB instruction
TEAB instruction
TABE instruction
TBA instruction
Register B
Register A
Register B
Register A
Register E
CYA3 A2 A1 A0
A0
CYA3 A2 A1
<Rotation>
RAR instruction
<Set>
SC instruction
<Clear>
RC instruction
Specifying address
TABP p instruction
p6 p5 p4
p3 p2 p1 p0
PCH
DR2DR1DR0 A3 A2 A1 A0
PCL
Immediate field
value p
The contents of
register D
ROM
840
Middle-order 4 bits
Low-order 4bits
Register A (4)
Register B (4)
The contents of
register A



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