4501 datasheet(39/116 Pages) RENESAS

39 / 116 page

4501 Group

Rev.3.01

2005.02.07

page 39 of 112

REJ03B0104-0301

• Program counter (PC) ..........................................................................................................

Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE) ..................................................................................................

• Power down flag (P) .............................................................................................................

• External 0 interrupt request flag (EXF0) ..............................................................................

• Interrupt control register V1 ..................................................................................................

• Interrupt control register V2 ..................................................................................................

• Interrupt control register I1 ...................................................................................................

• Timer 1 interrupt request flag (T1F) .....................................................................................

• Timer 2 interrupt request flag (T2F) .....................................................................................

• Watchdog timer flags (WDF1, WDF2) ..................................................................................

• Watchdog timer enable flag (WEF) ......................................................................................

• Timer control register W1 .....................................................................................................

• Timer control register W2 .....................................................................................................

• Timer control register W6 .....................................................................................................

• Clock control register MR .....................................................................................................

• Key-on wakeup control register K0 ......................................................................................

• Key-on wakeup control register K1 ......................................................................................

• Key-on wakeup control register K2 ......................................................................................

• Pull-up control register PU0 .................................................................................................

• Pull-up control register PU1 .................................................................................................

• Pull-up control register PU2 .................................................................................................

• A/D conversion completion flag (ADF) .................................................................................

• A/D control register Q1 .........................................................................................................

• Carry flag (CY) ......................................................................................................................

• Register A .............................................................................................................................

• Register B .............................................................................................................................

• Register D .............................................................................................................................

• Register E .............................................................................................................................

• Register X .............................................................................................................................

• Register Y .............................................................................................................................

• Register Z .............................................................................................................................

• Stack pointer (SP) ................................................................................................................

• Oscillation clock ..................................................................... On-chip oscillator (operating)

• Ceramic resonator circuit ..................................................................................... Operating

• RC oscillation circuit ...................................................................................................... Stop

“✕” represents undefined.

Fig. 36 Internal state at reset

✕✕

(2) Internal state at reset

Figure 36 shows internal state at reset (they are the same after sys-

tem is released from reset). The contents of timers, registers, flags

and RAM except shown in Figure 36 are undefined, so set the ini-

tial value to them.

000

0000

000

(Interrupt disabled)

(Prescaler and timer 1 stopped)

(Timer 2 stopped)

✕✕

✕✕✕

✕✕

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