HD404612FS datasheet(23/91 Pages) RENESAS

23 / 91 page

HD404618 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt

processing and set by the RTNI instruction, as shown in table 4.

Table 4 Interrupt Enable Flag

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

0, INT1): Specified by port mode register A (PMRA: $004).

The

INT

1 input can be used as a clock signal input to timer B.

Timer B increments at each falling edge of

the

INT

1 input.

When using

INT

1 as a timer B external event input, external interrupt mask IM1 must be

set to prevent the

INT

1 interrupt request from being accepted (see table 6).

To detect the edge of

INT

0 or INT1, more than two instruction cycle times are required (2tcyc or 2tsubcyc).

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the falling edge of the

INT

0 and INT1 inputs as shown in table 5.

Table 5 External Interrupt Request Flags

IF0, IF1

Interrupt Request

0No

Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests

caused by the corresponding external interrupt request flags, as shown in table 6.

Table 6 External Interrupt Masks

IM0, IM1

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A as shown in

table 7.

Table 7 Timer A Interrupt Request Flag

IFTA

Interrupt Request

0No

Yes

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