HD404612FS datasheet(58/91 Pages) RENESAS

58 / 91 page

HD404618 Series

Liquid Crystal Display (LCD)

The MCU has an LCD controller and driver which drive 4 common signal pins and 32 segment signal pins.

The controller consists of a RAM area in which display data is stored, a display control register (LCR), and

a duty/clock control register (LMR), as shown in figure 37.

Four duties and the LCD clock are program-controllable, and a built-in dual-port RAM ensures that display

data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz

oscillation clock is selected as the LCD clock source, the LCD can be used even in watch mode, in which

the system clock stops.

VCC

Power switch

GND

LCD

power

control

circuit

LCD

common

driver

Display on/off

Display

area

LCD duty/clock

control

(LMR: $014)

(Dual-port

RAM)

LCD

control

(LCR: $013)

LCD

segment

driver

LCD

clock

$050

$06F

RAM area

Duty cycle selection

Clock selection

LCD

clock

SEG32

SEG2

SEG1

COM4

COM3

COM2

COM1

Divided system clock

output (CL1–CL3)

Divided 32-kHz clock

output (CL0)

LCD: Liquid crystal display

Figure 35 Liquid Crystal Display Block Diagram

LCD Data Area and Segment Data ($050– $06F): Figure 36 shows the configuration of LCD RAM

area. Each bit of the storage area corresponds to one of four types of duties. If data is written to an area

corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display

data.

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