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HD151TS206SS датащи(PDF) 18 Page - Renesas Technology Corp

номер детали HD151TS206SS
подробное описание детали  Mother Board Clock Generator for Intel P4 Chipset (Springdale)
PDF  34 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD151TS206SS датащи(HTML) 18 Page - Renesas Technology Corp

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HD151TS206SS
Rev.1.00, Apr.28.2003, page 18 of 34
I
2C Controlled Register Bit Map (cont.)
Byte23 Control Register
Bit
Description
Contents
Type
Default
Note
7
Watchdog Enable Control Bit
0 = Disable, Pin22 = 3V66_0 output
1 = Enable, Pin22 = RESET# output
R/W
0
6
RESET# Reverse Control Bit
0 = Normal , 1 = Reverse
R/W
0
5
Watchdog Timer Count Bit3
R/W
1
4
Watchdog Timer Count Bit2
R/W
0
3
Watchdog Timer Count Bit1
R/W
0
2
Watchdog Timer Count Bit0
These 4 bits corresponds to how many
watchdog timer will wait from becoming
“Alarm mode” (B23[0] = 1) to outputting
RESET# pin to “Low”.
Default is 586ms x8 = 4.7s at Power
ON
R/W
0
1
Backup Frequency Select Bit
0 = B10[4:0], 1 = B11[4:0]
When SAFE_F# is “Low” , frequency
mode is changed to the predefined
frequency mode decided by B10[4:0] or
B11[4:0].
R/W
0
0
Watchdog Status Bit
0 = Normal mode, 1 = Alarm mode
R/W
0
Byte24 Control Register
Bit
Description
Contents
Type
Default
Note
7
Reserved
R/W
0
6
Reserved
R/W
0
5
Reserved
R/W
0
4
Reserved
R/W
0
3
Reserved
R/W
0
2
Reserved
R/W
0
1
Reserved
R/W
0
0
Reserved
R/W
0



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