HD151TS206SS datasheet(5/34 Pages) RENESAS

5 / 34 page

HD151TS206SS

Rev.1.00, Apr.28.2003, page 5 of 34

Pin Descriptions (cont.)

Pin name

No.

Type

Description

**SEL100_200/PCI_4

INPUT/OUTPUT

Latched select input for SRC output.

1 = 200 MHz, 0 = 100 MHz

/PCI clock 3.3 V output. 33 MHz clock divided down

from 3V66.

**SEL33_25/PCI_5

INPUT/OUTPUT

Latched select input for PCI5 output.

1 = 25 MHz, 0 = 33 MHz

/PCI clock 3.3 V output. 33 MHz clock divided down

from 3V66.

*PWRDWN#

/SAFE_FREQ

INPUT

Power down pin. All circuits will be powered down.

Asynchronous active low input pin used to power

down the device into low power state. The internal

clocks are disabled and VCO and the crystal are

stopped.

When Byte15 bit5 = 1 Safe frequency input select.

Real time input for frequency jump. Driving this input

'LOW' will cause output to jump to predefined IIC

frequency location.

**SEL48_24/48_24MHz 21

INPUT/OUTPUT

Latched select input for 48_24 MHz output

1 = 24 MHz, 0 = 48 MHz / 48_24 MHz clock 3.3 V

output.

**FS3/48MHz

INPUT/OUTPUT

Frequency select latch input pin.

3.3 V Fixed 48 MHz DOT clock output.

**SEL66_48

/3V66_3/VCH

INPUT/OUTPUT

Latched select input for 3V66/VCH output

1 = 48 MHz, 0 = 66.66 MHz. / 3V66 or VCH clock

output.

3V66_2,3V66_1

26,29

OUTPUT

3.3 V 66.66 MHz clock output.

3V66_0/RESET#

OUTPUT

3.3 V 66.66 MHz clock output / Real time system

reset signal for frequency gear ratio change or

watchdog timer timeout. This signal is active low and

selected by Mode latch input.

*SCLK

INPUT

Clock input for I

2C logic.

*SDATA

INPUT/OUTPUT

Data input and output for I

2C logic.

*VTT_PWRGD#

INPUT

Qualifying input that latches Frequency latch inputs.

When this input is at a logic low, Frequency latched.

SRC#

OUTPUT

“Complementary” clock of Differential Serial

Reference Clock.

SRC

OUTPUT

“True” clock of Differential Serial Reference Clock.

CPU[0:2]

39,42,

OUTPUT

“True” clocks of differential pair CPU clock.

CPU#[0:2]

38,41,

OUTPUT

“Complementary” clocks of differential pair CPU

clock.

IREF

INPUT

A precision resistor is attached to this pin which is

connected to internal current reference.

Note:

(*):

Those pins are 150 k

Ω internal pull-up.

(**):

Those pins are 150 k

Ω internal pull-down

HD151TS206SS датащи(PDF) 5 Page - Renesas Technology Corp

HD151TS206SS датащи(HTML) 5 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL