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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD151TS206SS датащи(PDF) 8 Page - Renesas Technology Corp |
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HD151TS206SS датащи(HTML) 8 Page - Renesas Technology Corp |
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8 / 34 page  HD151TS206SS Rev.1.00, Apr.28.2003, page 8 of 34 I 2C Controlled Register Bit Map (cont.) Table1 CPU Clock Power Management Truth Table Signal Pin PWRDWN# PWRDWN# Tristate Bit Byte2[5:3] Note CPU[2:0] 1 X Running CPU[2:0] 0 0 Driven @ Iref x2 See Note1 CPU[2:0] 0 1 Tristate Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA. Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω), Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω) Table2 SRC Clock Power Management Truth Table Signal Pin PWRDWN# PWRDWN# Tristate Bit Byte2[7] Note SRC 1 X Running SRC 0 0 Driven @ Iref x2 See Note1 SRC 01Tristate Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA. Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω), Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω) Byte3 Control Register Bit Description Contents Type Default Note 7 Reserved RW 1 6 Reserved RW 1 5 PCI_5 Output enable 0 = Disabled, 1 = Enabled RW 1 4 PCI_4 Output enable 0 = Disabled, 1 = Enabled RW 1 3 PCI_3 Output enable 0 = Disabled, 1 = Enabled RW 1 2 PCI_2 Output enable 0 = Disabled, 1 = Enabled RW 1 1 PCI_1 Output enable 0 = Disabled, 1 = Enabled RW 1 0 PCI_0 Output enable 0 = Disabled, 1 = Enabled RW 1 Byte 4 Control Register Bit Description Contents Type Default Note 7 Reserved RW 0 6 48_24MHz Output Enable 0 = Disabled, 1 = Enabled RW 1 5 Reserved RW 0 4 Reserved RW 0 3 Reserved RW 0 2 PCIF_2 Output enable 0 = Disabled, 1 = Enabled RW 1 1 PCIF_1 Output enable 0 = Disabled, 1 = Enabled RW 1 0 PCIF_0 Output enable 0 = Disabled, 1 = Enabled RW 1 |
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