M306V2EEFS datasheet(247/271 Pages) RENESAS

247 / 271 page

Rev.1.40

Oct 06, 2004 page 247 of 269

M306V2ME-XXXFP, M306V2EEFP

3.9 Interrupts

(1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number

and interrupt request level) in the interrupt sequence.

The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.

Reading address 0000016 by software sets enabled highest priority interrupt source request bit to

“0”.

Though the interrupt is generated, the interrupt routine may not be executed.

Do not read address 0000016 by software.

(2) Setting the stack pointer

• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an

interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to

set a value in the stack pointer before accepting an interrupt.

(3) External interrupt

_______

• When the polarity of the INT0 and INT1 pins is changed, the interrupt request bit is sometimes set

to “1.” After changing the polarity, set the interrupt request bit to “0.”

(4) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point that does not generate the interrupt

request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt

control register after the interrupt is disabled. The program examples are described as follow:

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP

FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted

before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the

interrupt control register is rewritten due to effects of the instruction queue.

• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the

interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-

ated. This will depend on the instruction. If this creates problems, use the below instructions to change

the register.

Instructions : AND, OR, BCLR, BSET

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