C511 datasheet(28/128 Pages) SIEMENS

28 / 128 page

External Bus Interface

Semiconductor Group

4-1

External Bus Interface

The SAB-C511/513 microcontrollers allow external memory expansion. The functionality and

implementation of the external bus interface is identical to the common interface for the 8051

architecture with one exception : if the SAB-C511/513 is used in systems with no external memory

the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register,

the ALE signal will be gated and no more generated externally. This feature reduces RFI emmisions

of the system.

4.1

Accessing External Memory

It is possible to distinguish between accesses to external program memory and external data

memory or other peripheral components respectively. This distinction is made by hardware.

Accesses to external program memory use the signal PSEN (program store enable) as a read

strobe. Accesses to external data memory use RD and WR (alternate functions of P3.7 and P3.6)

to strobe the memory. Port 0 and port 2 (with exceptions) are used to provide data and address

signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are

described.

Fetches from external program memory always use a 16-bit address. Accesses to external data

memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).

4.1.1 Role of P0 and P2 as Data/Address Bus

When used for accessing external memory, port 0 provides the data byte time-multiplexed with the

low byte of the address. In this state, port 0 is disconnected from its own port latch and the address/

data signal drives both FETs in the port 0 output buffers. Thus, in this application the port 0 pins are

not open-drain outputs and do not require external pullup resistors.

During any access to external memory, the CPU writes FFH to the port 0 latch (the special function

Whenever a 16-bit address is used (MOVX @DPTR), the high byte of the address comes out on

port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are

disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have

to contain 1s, and the contents of the port 2 SFR are not modified. If the XRAM is enabled (only

SAB-C513A/A-H) at 16-bit address accesses with an address value within the XRAM address

space, no external bus cycle will be seen, but the internal XRAM will be accessed.

If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins

throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2

pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and

not only for two oscillator periods. If the XRAM is enabled at the SAB-C513A/A-H no external bus

cycle will be seen regardless of the address.

C511 датащи(PDF) 28 Page - Siemens Semiconductor Group