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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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C511 датащи(PDF) 91 Page - Siemens Semiconductor Group |
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C511 датащи(HTML) 91 Page - Siemens Semiconductor Group |
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91 / 128 page  Semiconductor Group 7-4 Interrupt System 7.2 Interrupt Control Bits 7.2.1 Interrupt Enables Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the SFR IE (Interrupt Enable). This register also contains the global disable bit EA, which can be cleared/set to disable/enable all interrupts at once. Special Function Registers IE (Address A8H) Reset Value : 00H Bit Function EA Disables all Interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ESSC SSC Interrupt Enable If ESSC = 0 the interrupt of the synchronous serial channel is disabled ET2 Timer 2 Interrupt Enable. If ET2 = 0, the timer 2 interrupt is disabled. ES USART Serial Channel Interrupt Enable (C513/C513A/C513A-H only) If ES = 0, the serial channel interrupt is disabled. ET1 Timer 1 Overflow Interrupt Enable. If ET1 = 0, the timer 1 interrupt is disabled. EX1 External Interrupt 1 Enable. If EX1 = 0, the external interrupt 1 is disabled. ET0 Timer 0 Overflow Interrupt Enable. If ET0 = 0, the timer 0 interrupt is disabled. EX0 External Interrupt 0 Enable. If EX0 = 0, the external interrupt 0 is disabled. EA ESSC ET2 ES A8H IE Bit No. 7 65 43 21 0 MSB LSB ET1 EX1 ET0 EX0 |
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