C511 datasheet(85/128 Pages) SIEMENS

85 / 128 page

Semiconductor Group

6-52

On-Chip Peripheral Units

6.4.8.3

Status Register SCF

This bit addressable register contains the status bits.

Special Function Registers SCF (Address F8H)

Reset Value : XXXXXX00B

Bit

Function

–

Not implemented. Reserved for future use. During reads these bits

will be undefined.

WCOL

Write Collision Detect

If WCOL is set it indicates that an attempt was made to write to the

shift register STB while a data transfer was in progress and not fully

completed. This bit will be set at the trailing edge of the write signal

during the erronous write attempt.

This bit can be reset in two different ways :

1. writing a "0" to the bit (bit access, byte access or read-modify-

write access);

2. by reading the bit or the status register, followed by a write

access to STB.

If bit WCEN in the SCIEN register is set, an interrupt request will be

generated if WCOL is set.

Transfer Completed

If TC is set it indicates that the last transfer has been completed. It is

set with the last sample clock edge of a reception process.

This bit can be reset in two different ways:

1. writing a "0" to the bit (bit access, byte access or read-modify-

write access) after the receive buffer register SRB has been read;

2. by reading the bit or the status register, followed by a read

access to SRB.

If bit TCEN in the SCIEN register is set, an interrupt request will be

generated if TC is set.

–

–––

F8H

SCF

Bit No.

MSB

LSB

–

WCOL

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