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TMS320DM335 датащи(PDF) 1 Page - Texas Instruments

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номер детали TMS320DM335
подробное описание детали  Digital Media System-on-Chip (DMSoC)
PDF  156 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM335 датащи(HTML) 1 Page - Texas Instruments

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TMS320DM335 Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM335
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS528 – JULY 2008
DDR2 and mDDR SDRAM 16-bit wide EMIF
• High-Performance Digital Media
With 256 MByte Address Space (1.8-V I/O)
System-on-Chip
Asynchronous16-/8-bit Wide EMIF (AEMIF)
135-, 216-, and 270-MHz ARM926EJ-S™
• Flash Memory Interfaces
Clock Rate
NAND (8-/16-bit Wide Data)
Fully Software-Compatible With ARM9
OneNAND(16-bit Wide Data)
• ARM926EJ-S Core
• Flash Card Interfaces
Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
Two Multimedia Card (MMC) / Secure
Digital (SD/SDIO)
DSP Instruction Extensions and Single
Cycle MAC
SmartMedia
ARM® Jazelle® Technology
• Enhanced Direct-Memory-Access (EDMA)
EmbeddedICE-RT™ Logic for Real-Time
Controller (64 Independent Channels)
Debug
• USB Port with Integrated 2.0 High-Speed PHY
• ARM9 Memory Architecture
that Supports
16K-Byte Instruction Cache
USB 2.0 Full and High-Speed Device
8K-Byte Data Cache
USB 2.0 Low, Full, and High-Speed Host
32K-Byte RAM
• Three 64-Bit General-Purpose Timers (each
configurable as two 32-bit timers)
8K-Byte ROM
• One 64-Bit Watch Dog Timer
Little Endian
• Three UARTs (One fast UART with RTS and
• Video Processing Subsystem
CTS Flow Control)
Front End Provides:
• Three Serial Port Interfaces (SPI) each with
• Hardware IPIPE for Real-Time Image
two Chip-Selects
Processing
• One Master/Slave Inter-Integrated Circuit (I2C)
• Up to 14-bit CCD/CMOS Digital Interface
Bus®
• 16-/8-bit Generic YcBcR-4:2 Interface
• Two Audio Serial Port (ASP)
(BT.601)
I2S and TDM I2S
• 10-/8-bit CCIR6565/BT655 Interface
AC97 Audio Codec Interface
• Up to 75-MHz Pixel Clock
S/PDIF via Software
• Histogram Module
Standard Voice Codec Interface (AIC12)
• Resize Engine
SPI Protocol (Master Mode Only)
Resize Images From 1/16x to 8x
Separate Horizontal/Vertical Control
• Four Pulse Width Modulator (PWM) Outputs
Two Simultaneous Output Paths
• Four RTO (Real Time Out) Outputs
Back End Provides:
• Up to 104 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions)
• Hardware On-Screen Display (OSD)
• Composite NTSC/PAL video encoder
• On-Chip ARM ROM Bootloader (RBL) to Boot
output
From NAND Flash, MMC/SD, or UART
• 8-/16-bit YCC and Up to 18-Bit RGB666
• Configurable Power-Saving Modes
Digital Output
• Crystal or External Clock Input (typically
• BT.601/BT.656 Digital YCbCr 4:2:2
24 MHz or 36 MHz)
(8-/16-Bit) Interface
• Flexible PLL Clock Generators
• Supports digital HDTV (720p/1080i)
• Debug Interface Support
output for connection to external
IEEE-1149.1 (JTAG)
encoder
Boundary-Scan-Compatible
• External Memory Interfaces (EMIFs)
ETB™ (Embedded Trace Buffer™) with
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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