TMS320DM335 datasheet(73/156 Pages) TI

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3.5.5

Peripheral Clocking Considerations

3.5.5.1 Video Processing Back End Clocking

3.5.5.2 USB Clocking

TMS320DM335

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS528 – JULY 2008

3.5.4.2.2 DM335-270 PLL2 (36 MHz reference)

All supported clocking configurations for DM335-270 PLL2 with 36 MHz reference clock are shown in

Table 3-5.

Table 3-13. PLL2 Supported Clocking Configurations for DM335-270 (36 MHz reference)

PREDIV

PLLM

POSTDIV

PLL2 VCO

DDR PHY

DDR Clock

(/n programmable)

(m programmable)

(/1 fixed)

(MHz)

PLLDIV1

SYSCLK1

DDR_CLK

(/1 fixed)

(MHz)

bypass

144

432

216

138

414

207

132

396

198

126

378

189

120

360

180

114

342

171

108

324

162

102

306

153

288

144

133

266

133

150

200

100

120

160

The Video Processing Back End (VPBE) is a sub-module of the Video Processing Subsystem (VPSS).

The VPBE is designed to interface with a variety of LCDs and an internal DAC module. There are two

asynchronous clock domains in the VPBE: an internal clock domain and an external clock domain. The

internal clock domain is driven by the VPSS clock (PLL1 SYSCLK4). The external clock domain is

configurable; you can select one of five source:

• 24 MHz crystal input at MXI1

• 27 MHz crystal input at MXI2 (optional feature, not typically used)

• PLL1 SYSCLK3

• EXTCLK pin (external VPBE clock input pin)

• PCLK pin (VPFE pixel clock input pin)

See the TMS320DM335 Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE)

Reference Guide (literature number SPRUFX9) for complete information on VPBE clocking.

The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of

the USB PHY.

NOTE

For proper USB 2.0 function, SYSCLK2 must be greater than 60 MHz.

The USB PHY takes an input clock that is configurable by the USB PHY clock source bits (PHYCLKSRC)

in the USB PHY control register (USB_PHY_CTL) in the System Control Module. When a 24 MHz crystal

is used at MXI1/MXO1, set PHYCLKSRC to 0. This will present a 24 MHz clock to the USB PHY. When a

36 MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to 1. This will present a 12 MHz clock (36 MHz

divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12

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