56F827 datasheet(39/60 Pages) FREESCALE

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Serial Peripheral Interface (SPI) Timing

56F827 Technical Data, Rev. 12

Freescale Semiconductor

3.9 Serial Peripheral Interface (SPI) Timing

1. Parameters listed are guaranteed by design.

Table 3-12 SPI Timing1

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

—

Figures

3-20, 3-21,

3-22, 3-23

Enable lead time

Master

Slave

tELD

—

Figure 3-23

Enable lag time

Master

Slave

tELG

—

100

—

Figure 3-23

Clock (SCLK) high time

Master

Slave

tCH

—

Figures

3-20, 3-21,

3-22, 3-23

Clock (SCLK) low time

Master

Slave

tCL

24.1

—

Figures

3-20, 3-21,

3-22, 3-23

Data set-up time required for inputs

Master

Slave

tDS

—

Figures

3-20, 3-21,

3-22, 3-23

Data hold time required for inputs

Master

Slave

tDH

—

Figures

3-20, 3-21,

3-22, 3-23

Access time (time to data active from high-impedance state)

Slave

4.8

Figure 3-23

Disable time (hold time to high-impedance state)

Slave

3.7

15.2

Figure 3-23

Data Valid for outputs

Master

Slave (after enable edge)

tDV

—

4.5

20.4

Figures

3-20, 3-21,

3-22, 3-23

Data invalid

Master

Slave

tDI

—

Figures

3-20, 3-21,

3-22, 3-23

Rise time

Master

Slave

—

11.5

10.0

Figures

3-20, 3-21,

3-22, 3-23

Fall time

Master

Slave

—

9.7

9.0

Figures

3-20, 3-21,

3-22, 3-23

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