RMLD232UAW datasheet(35/50 Pages) EMLSI

35 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

NOTES:

1.Input Setup/Hold Slew Rate Derating

This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ .

2. Minimum 5CLK of tDAL(=tWP +tRP) is required because it need minimum 2 CLKs for tWP and minimum 3 CLKs for tRP.

3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25 ).

tAC(max) value is measured at the low Vdd(1.7V) and cold temperature(-25 ).

tAC is measured in the device with half driver strength(CL=10pF) and under the AC output load condition(fig.2 in next Page).

4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High-Z to

logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High

at this time, depending on tDQSS.

5. I/O Setup/Hold Slew Rate Derating

This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ .

6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating

This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is

calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1=1.0V/

and slew rate 2=0.8V/ , then the Delta Rise/Fall

Rate=-0.25 /V.

7. Maximum burst refresh cycle : 8

Input Setup/Hold Slew Rate

tIS

tIH

(V/

)

( )

1.0

0.8

+50

0.6

+100

I/O Setup/Hold Slew Rate

tDS

tDH

(V/ )

( )

1.0

0.8

+75

0.6

+150

Delta Rise/Fall Rate

tDS

tDH

( /V)

( )

0.25

+50

0.5

+100

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