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RMLD232UAW датащи(PDF) 12 Page - Emerging Memory & Logic Solutions Inc

номер детали RMLD232UAW
подробное описание детали  2M x 32 bit Low Power DDR SDRAM
PDF  50 Pages
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производитель  EMLSI [Emerging Memory & Logic Solutions Inc]
домашняя страница  http://www.emlsi.com
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RMLD232UAW датащи(HTML) 12 Page - Emerging Memory & Logic Solutions Inc

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12
Rev 0.7
64Mb Low Power DDR SDRAM
Advanced
Essential Functionality for DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the SDRAM such that the burst read command is issued by asserting
CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address
inputs (A0~A9) determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst
length(2, 4, 8, 16). The first output data is available after the CAS Latency from the READ command, and the consecutive data are
presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is completed.
0
1
2
3
4
5
6
7
8
CK
CK
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
tAC
tRPRE
Preambel
Postamble
Dout 0 Dout 1 Dout 2 Dout 3
CAS Latency=3
DQS
DQs
Figure.5 Burst read operation timing
< Burst Length=4, CAS Latency=3 >
tRPST



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