32

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

STABLE is defined as inputs stable at a HIGH or LOW level;

SWITCHING is defined as:

-address and command: inputs changing between HIGH and LOW once per two clock cycles

-data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.

AC operating Conditions & Timing Specification

NOTE :

1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, all inputs

V

1

Input Low (Logic 0) Voltage, all inputs

-0.3

V

1

Input Crossing Point Voltage, CK and CK inputs

V

2