14

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Read Interrupted by a Read

A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is inter-

rupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command

continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from

the interrupting Read command appears. Read to Read interval is minimum 1 Clock.

Read Interrupted by a Write & Burst Stop

To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by

placing the DQs(Output drivers) in a high impedance state. To insure the DQs are tri-stated one cycle before the beginning of the

write operation, Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the

Write command.

The following functionality establishes how a Write command may interrupt a Read burst.

1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ

bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command

=RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].

2. It is illegal for a Write command to interrupt a Read with autoprecharge command.

0

1

2

3

4

5

6

7

8

CK

CK

Command

NOP

NOP

NOP

NOP

NOP

NOP

NOP

DQS

DQs

Figure.7 Read interrupted by a read timing

< Burst Length=4, CAS Latency=3 >

READ A

READ B

Preamble

CAS Latency=3

0

1

2

3

4

5

6

7

8

CK

CK

Command

NOP

NOP

NOP

Burst Stop

NOP

NOP

DQS

DQs

Figure.8 Read interrupted by a Write and burst stop timing

< Burst Length=4, CAS Latency=3 >

READ

WRITE

Dout 0 Dout 1

Preamble

CAS Latency=3

Din 0

Din 1 Din 2 Din 3