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ST92163 датащи(PDF) 216 Page - STMicroelectronics |
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ST92163 датащи(HTML) 216 Page - STMicroelectronics |
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216 / 224 page ![]() 216/224 ST92163 - ELECTRICAL CHARACTERISTICS SCI TIMING TABLE (VDD = 3.0 - 5.5V (1),T A =0°C+ 70°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) (1) 3.0 - 4.0V voltage range is only available on devices with suffix L or V, with different frequency limitatio ns (L: 8 MHz, V: 16 MHz) Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. SCI TIMING N ° Symbol Parameter Conditio n Value Unit Min Max FRxCKIN Frequency of RxCKIN 1x mode fINTCLK /8 MHz 16x mode fINTCLK /4 MHz TwRxCKIN RxCKIN shortest pulse 1x mode 4 x Tck s 16x mode 2 x Tck s FTxCKIN Frequency of TxCKIN 1x mode fINTCLK /8 MHz 16x mode fINTCLK /4 MHz TwTxCKIN TxCKIN shortest pulse 1x mode 4 x Tck s 16x mode 2 x Tck s 1TsDS DS (Data Stable) before rising edge of RxCKIN 1x mode reception with RxCKIN Tck / 2 ns 2TdD1 TxCKIN to Data out delay Time 1x mode transmission with external clock CLoad < 50pF 2.5 x Tck ns 3TdD2 CLKOUT to Data out delay Time 1x mode transmission with CLKOUT TBD ns |
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