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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST92163 датащи(PDF) 214 Page - STMicroelectronics |
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ST92163 датащи(HTML) 214 Page - STMicroelectronics |
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214 / 224 page  214/224 ST92163 - ELECTRICAL CHARACTERISTICS WATCHDOG TIMING TABLE (VDD = 3.0 - 5.5V (1) ,T A =0°C+ 70°C, CLoad = 50pF, fINTCLK = 24MHz, Push-pull output configuration, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, watchdog prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and maximum prescaler value and minimum and maximum counter value. (1) 3.0 - 4.0V voltage range is only available on devices with suffix L or V, with different frequency limitatio ns (L: 8 MHz, V: 16 MHz) Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. Psc = Watchdog Prescaler Register content (WD TPR): from 0 to 255 Cnt = Watchdog Couter Registers content (WDTRH,WD TRL): from 0 to 65535 TWDIN = Watchdog Input signal period (WDIN) WATCHDOG TIMING N ° Symbol Parameter Value (Note) Unit Formula Min Max 1 TwWDOL WDOUT Low Pulse Width 4 x (Psc+1) x (Cnt+1) x Tck 167 2.8 ns s (Psc+1) x (Cnt+1) x TWDIN with TWDIN ≥ 8 x Tck 333 ns 2 TwWDOH WDOUT High Pulse Width 4 x (Psc+1) x (Cnt+1) x Tck 167 2.8 ns s (Psc+1) x (Cnt+1) x TWDIN with TWDIN ≥ 8 x Tck 333 ns 3 TwWDIL WDIN High Pulse Width ≥ 4 x Tck 167 ns 4 TwWDIH WDIN Low Pulse Width ≥ 4 x Tck 167 ns |
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