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ST7261 датащи(PDF) 20 Page - STMicroelectronics

номер детали ST7261
подробное описание детали  LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, ROM MEMORY, LVD, WDG, TIMER
PDF  80 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST7261 датащи(HTML) 20 Page - STMicroelectronics

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6.6 Interrupt Register
INTERRUPT REGISTER 1 (ITRFRE1)
Address: 0008h - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = ITiE
Interrupt Enable
0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.
Note: The corresponding interrupt is generated
when:
– a rising edge occurs on the IT5/IT6 pins
– a falling edge occurs on the IT1, 2, 3, 4, 7 and 8
pins
INTERRUPT REGISTER 2 (ITRFRE2)
Address: 0039h - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = CTL[3:2]
IT[12:11] Interrupt Sensitivity
These bits are set and cleared by software. They
are used to configure the edge and level sensitivity
of the IT12 and IT11 external interrupt pins (this
means that both must have the same sensitivity).
Bit 5:4 = CTL[1:0]
IT[10:9]1nterrupt Sensitivity
These bits are set and cleared by software. They
are used to configure the edge and level sensitivity
of the IT10 and IT9 external interrupt pins (this
means that both must have the same sensitivity).
Bit 3:0 = ITiE
Interrupt Enable
0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.
70
IT8E
IT7E
IT6E
IT5E
IT4E
IT3E
IT2E
IT1E
70
CTL3 CTL2 CTL1 CTL0 IT12E IT11E IT10E IT9E
CTL3
CTL2
IT[12:11] Sensitivity
0
0
Falling edge and low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
CTL1
CTL0
IT[10:9] Sensitivity
0
0
Falling edge and low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge



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