TDA7333N datasheet(27/36 Pages) STMICROELECTRONICS

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TDA7333N

Functional description

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3.9

I2C transfer mode

This interface consists of three lines: a serial data line (SDA), a bit clock (SCL), and a slave

address select (SA).

The interface is capable of operating up to 400 kbits/s. If during the setup the system clock

fsys is smaller then 8.55 MHz, then the max. I2C speed decreases linear (e.i. if fsys = 4.275

MHz then the maximum I2C speed is 200 kbits/s for setup).

Data transfers follow the format shown in Figure 10. After the START condition (S), a slave

address is sent. The address is 7 bits long followed by an eighth bit which is a data direction

bit (R/_W).

A zero indicates a transmission (WRITE), a one indicates a request for data (READ).

The slave address of the chip is set to 001000S, where S is the least significant bit of the

slave address set externally via the pin SA_DATAOUT. This allows to choose between two

addresses in case of conflict with another device of the radio set.

Each byte has to be followed by an acknowledge bit (SDA low).

Data is transferred with the most significant (MSB) bit first.

A data transfer is always terminated by a stop condition (P) generated by the master.

Figure 10.

I2C data transfer

3.9.1

Write transfer

Figure 11.

I2C write transfer

9 registers are available with write access (please refer to Section 3.8 for the meaning of

each bit).

To write registers, the external master must initiate the write transfer as described above,

then send the data to be written, and terminate the transfer by generating a stop condition.

1-7

SDA

SCL

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK/ACK

Slave address

rds_int

sinc4reg

testreg

rds_bd_ctrl

from master to slave

from slave to master

W = write mode

Slave address = 001000S ( where S is the level of the pin

SA_DATAOUT)

A = acknowledge bit

P = stop condition

S = start condition

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