TDA7333N datasheet(18/36 Pages) STMICROELECTRONICS

18 / 36 page

Functional description

TDA7333N

18/36

Figure 7.

RAM buffer usage

After power up, or after resynchronization by setting “ar_res” rds_int[5] to one, incoming

RDS blocks are stored in the RAM buffer when synchronization has been established

(Figure 8). But if the bit “syncw” rds_bd_ctrl[0] (refer to Section 3.8.6) is cleared, every

received RDS block is stored, also without synchronization. This means if the RDS is not

synchronized, every received consecutive 26 RDS data bits are treated as a RDS block.

Figure 8.

RAM buffer update depends on “syncw” bit rds_bd_ctrl[0]

The RAM buffer is used as a circular FIFO (Figure 9). If more than 24 blocks are written, the

oldest data will be overwritten. One level of the buffer consists of 4 bytes (2 information

bytes, 2 RDS data bytes). If less than 4 bytes of the RAM buffer are read out from the

master via the SPI or I2C interface, the buffer address will not be incremented.

rds_qu[7..0]

rds_corrp[7..0]

rds_bd_h[7..0]

rds_bd_l[7..0]

rds_bd_ctrl[7..0]

sinc4reg[7..0]

testreg[7..0]

rds_int[7..0]

INTERNAL REGISTERS

RAM BUFFER

(24 blocks)

I2C/SPI SHIFT REGISTER

SA_DATAOUT

(spi mode)

SDA_DATAIN

(i2c mode)

rds_qu[7..0]

rds_corrp[7..0]

rds_bd_h[7..0]

rds_bd_l[7..0]

rds_bd_ctrl[7..0]

sinc4reg[7..0]

testreg[7..0]

rds_int[7..0]

read access

(internal)

write access

(external)

pllreg4[7..0]

pllreg0[7..0]

pllreg4[7..0]

Block A

Block B

Block C

RDS data

bits

Write to RAM

Buffer if

"syncw" = 1

Write to RAM

Buffer if

"syncw" = 0

Synchro-

nization flag

"synch"

time

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