TDA7333N datasheet(13/36 Pages) STMICROELECTRONICS

13 / 36 page

TDA7333N

Functional description

13/36

Figure 4.

Demodulator block diagram

The module needs a fixed clock of 8.55 MHz. Optionally an 8.664 MHz clock may be used

by setting the corresponding bit in rds_bd_ctrl register (refer to Section 3.8.6).

In order to optimize the error correction in the group and block synchronization module, the

sensitivity level of the quality bit can be adjusted in four steps with “qsens” bits

rds_bd_ctrl[5:4]. Only bits marked as bad by the quality bit are allowed to be corrected in the

group and block synchronization module. If an error correction is done on a good marked

RDS bit, the “data_ok” bit rds_corrp[1] will not be set (refer to Section 3.8.3).

The RDS bit demodulator can be controlled by the bits 1-6 of rds_bd_ctrl register for

example to select 57 kHz PLL and 1187.5 Hz PLL time constant. This is useful in order to

achieve a fast synchronization after a program resp. frequency change (fast time constant)

and to get a maximum of noise immunity after synchronization (slow time constant).

The user may choose between 2 possibilities via bit rds_bd_ctrl[1]:

Hardware selected time constant - In this case both pll time constants are reset to

the fastest one, with a reset from the group and block synchronization module, or if

the software decides to resynchronize by setting “ar_res” rds_int[5] (refer to page

18). Then both PLLs increase automatically to the slowest time constant. This is

done in four steps within a total time of 215.6 ms (256 RDS clocks).

Software selected time constant - In this case the time constant of both PLL can

be selected individually by software (rds_bd_ctrl[4:2]). Four time constants (5 ms,

15 ms, 35 ms, 76 ms) can be set independently for 1187.5 Hz PLL and two time

constants (2 ms, 10 ms) for the 57 kHz PLL.

The sensitivity of the quality bit can be adjusted to four levels with the “qsens1” and “qsens0”

rds_bd_ctrl[6:5] bits. “qsens1 = 0” and “qsens0 = 0” means minimum sensitivity, “qsens1 =

1” and “qsens0 = 1” maximum sensitivity.

to RDS group and block synchronisation

module:

RDSCLK

RDSDAT

RDSQAL

AR_RES

mclk

(8,550 or 8,664 MHz)

MPX

Input-stage

(digital Filter )

ARI in-

dicator

57 kHz PLL

frequency

offset comp.

Clock Generator

Half Wave

Integrator

Half Wave

Extractor

RDS Quality

Extractor

RDS Data

Extractor

1187.5Hz

PLL

mclk

from RDS group and block synchronisation

module:

Sine comp.

Cosine comp.

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