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ADUCM310 датащи(PDF) 17 Page - Analog Devices |
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ADUCM310 датащи(HTML) 17 Page - Analog Devices |
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17 / 28 page ![]() ADuCM310 Data Sheet Rev. A Page 16 of 27 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit t CS0/tCS1 CS0/CS1 to SCLKx edge 10 ns t CSM CS0/CS1 high time between active periods SCLKx ns t SL SCLKx low pulse width (SPIxDIV1 + 1) × t HCLK 2 ns t SH SCLKx high pulse width (SPIxDIV1 + 1) × t HCLK 2 ns t DAV Data output valid after SCLKx edge 20 ns t DSU Data input setup time before SCLKx edge 10 ns t DHD Data input hold time after SCLKx edge 10 ns t DF Data output fall time 25 ns t DR Data output rise time 25 ns t SR SCLKx rise time 1 ns t SF SCLKx fall time 1 ns t DOCS Data output valid after CS0/CS1 edge 20 ns t SFS CS0/CS1 high after SCLKx edge 10 ns 1 For SPI0, x is 0, and for SPI1, x is 1 2 t HCLK is the divided system clock, UCLK/CLKCON1[2:0]. SCLKx (POLARITY = 0) SCLKx (POLARITY = 1) tSH tSL tSR tSF tSFS MISOx MOSIx MSB IN BIT 6 TO BIT 1 LSB IN tDHD tDSU MSB BIT 6 TO BIT 1 LSB tDOCS tDAV tDR tDF tCS0/tCS1 CS0/CS1 tCSM Figure 6. SPI Slave Mode Timing (Phase Mode = 0) |
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