ADUCM310 datasheet(10/28 Pages) AD

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Data Sheet

ADuCM310

Rev. A Page 9 of 27

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Gain Error Drift

Excluding internal reference drift

VDAC0, VDAC1, VDAC4, and

VDAC5

ppm/°C

VDAC2, VDAC3, VDAC6, and

VDAC7

ppm/°C

Output Impedance

VDAC0, VDAC1, VDAC4,

VDAC5, VDAC6, and VDAC7

Ω

VDAC2 and VDAC3

1.5

Ω

Short-Circuit Current

Measured with VDAC shorted to

ground and to associated power

supply

VDAC0 and VDAC1

±200

VDAC2 and VDAC3

±170

VDAC4 and VDAC5

±200

VDAC6 and VDAC7

±200

VDAC Outputs

Capacitive load up to 0.01 µF

Output Impedance

VDAC0, VDAC1, and VDAC4

to VDAC7

1.8

Ω

VDAC2 and VDAC3

1.2

Ω

Output Range

Buffer on

VDAC0 and VDAC1

0.15

DD –

600 mV

L = 75 Ω, 40 mA maximum, VOUT

maximum = 3 V

VDAC2 and VDAC3

NEG +

250 mV

−0.15

L = 500 Ω, 10 mA maximum, VOUT

maximum = −5 V, gain = −2.25 V

VDAC4 and VDAC5

0.15

DD –

300 mV

L = 300 Ω, 10 mA maximum, VOUT

maximum = 3 V

VDAC6

0.15

VDACV

DD −

250 mV

L = 500 Ω, 10 mA maximum, VOUT

maximum = 5 V

VDAC7

0.15

VDACV

DD −

700 mV

L = 100 Ω, 50 mA maximum, VOUT

maximum = 5 V

DAC AC CHARACTERISTICS

Slew Rate

VDAC0, VDAC1, VDAC4, and

VDAC5

V/µs

VDAC2, VDAC3, and VDAC6

1.1

V/µs

Voltage Output Settling Time

µs

Load =100 pF

0.05

Load = 0.01 µF

Digital-to-Analog Glitch Energy

nV/sec

1 LSB change at major carry

(DACxDAT register change from

0x07FF0000 to 0x08000000)

AC PSRR 100 Hz

VDAC0, VDAC1, VDAC4, and

VDAC5

VDAC2 and VDAC3

VDAC6 and VDAC7

AC PSRR 1 kHz

VDAC0, VDAC1, VDAC4, and

VDAC5

VDAC2 and VDAC3

VDAC6 and VDAC7

POWER-ON RESET (POR)

Refers to voltage at DVDD pin

POR Trip Level

2.81

2.85

2.9

Power-on level

2.74

2.79

2.83

Power-down level

POR Hysteresis

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